Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is currently a popular type of planar display. Low Temperature Poly-Silicon (LTPS) technique is a new generation of TFT display, which provides a higher resolution and a better picture display quality. The basic structure of a TFT-LCD includes a liquid crystal panel composed of two substrates. A liquid crystal capacitance can be created by applying electrical field to the substrates, so as to control orientation of the liquid crystal. In order to prevent image degradation due to use of unidirectional electrical field for a long time, the polarity of a data voltage relative to a common voltage needs to be frequently inverted. For a small-size LCD, in order to reduce its power consumption, a column inversion mode is typically adopted. However, when compared with a point inversion mode, the column inversion mode is significantly inferior in terms of vertical cross-interference.
FIG. 1 is a schematic diagram showing a structure of a conventional pixel unit driving circuit. As shown in FIG. 1, the panel components include a plurality of scan signal lines G1-Gn (among which only the scan signal lines Gi-Gi+4 are shown in FIG. 1 for illustration), a plurality of data lines D1-Dm (among which only the data lines Dj-Dj+4 are shown in FIG. 1 for illustration), and pixel units connected to the scan signal lines and the data lines. The scan signal lines and the data lines are cross-connected to the switch elements of the pixel units and are arranged in a matrix form, so as to constitute a pixel unit driving circuit. Typically, the switch elements for the pixel units formed by an LTPS array are NMOS transistors, for which the driving method is shown in FIG. 1. An output voltage of a gate (scan signal line) can only have two possible values: an on voltage (high level) t1 and an off voltage (low level) t2. For each frame, T, of picture, the switch elements are on and the pixels in row G1 are charged when the high level t1 is outputted at G1, and the switch element are off and the pixels in row G1 are maintained when the low level t2 is outputted at G1. The high level is outputted at G2 when the low level is outputted at G1. Similar operation modes apply to rows G2-Gm. However, when the pixels in row G1 are being charged, the data signals on the data lines D1-Dn will be applied to all the pixels in rows G1-Gm. While the switch elements are off, the capacitive coupling effect between the data lines and the pixel electrodes will affect the maintained state of the pixels in rows G2-Gm, thereby causing a vertical cross-interference in the displayed picture. This problem becomes even worse at a higher resolution.
FIG. 2 is a schematic diagram showing a basic structure of a pixel unit. As shown in FIG. 2, each pixel unit includes a switch element, Q, connected to the one of the scan signal lines G1-Gn and one of the data lines D1-Dm. The switch elements can be typically NMOS transistors, or alternatively PMOS transistors.
In the conventional pixel unit shown in FIG. 1 and FIG. 2, the polarity of the data voltage relative to the common voltage needs to be frequently inverted. Such column inversion mode has a poor performance in terms of vertical cross-interference.